Backplane bus system including a plurality of nodes

ABSTRACT

A system for communicating between a plurality of nodes in a computer, each node including logic circuitry for transmitting and receiving data. The subject system includes (1) a backplane bus for carrying the data between the nodes, (2) a driver in each node and a current source circuit coupled to the bus which drive the bus in parallel to decrease the transition time of the data transmitted onto the bus, and (3) coupling resistors individually coupling the bus to the driver in each node and providing impedance matching between the bus and nodes and permitting driver overlap at the bus so that the higher speed and lower power dissipation occurs. In the preferred embodiment, CMOS logic circuitry is utilized and resistors are used to terminate the ends of the bus to the supply voltages.

This application is a continuation of application Ser. No. 044,479,filed May 1, 1987, now abandoned.

I. BACKGROUND OF THE INVENTION

The present invention relates to data processing systems and, inparticular, to a system bus for use in such systems. The presentinvention is particularly advantageous in that the subject bus ischaracterized by high performance, low power consumption and reducedspace used for bus logic on a printed circuit board, relative to priorart devices.

In computers and other data processing devices, a bus is commonlyemployed to interconnect the various elements of the device. Forexample, a central processing unit is typically connected to memorycomponents, input/output devices, etc. via a bus capable of carrying thesignals associated with operation of each element. These signalsinclude, for example, data signals, clock signals and other controlsignals. The bus must be capable of carrying such signals to all of thecomponents coupled to it so that the desired operation can be carriedout by the computer system.

Because the bus is utilized in virtually every operation performed bythe computer system, it is a key element whose characteristics have amajor impact on overall performance of the system. For example, speed ofoperation is limited to a degree since many of the signals within thecomputer must be transmitted via the bus to the appropriate component;thus, the speed at which the bus is capable of responding to andcarrying data is a critical consideration.

A further critical aspect of bus operation relates to the consumption ofpower by the bus. Since the bus is used in nearly every operation, it isimportant that the bus and associated interface logic consume as littlepower as possible in its functioning. Prior art attempts to reduce powerconsumption have usually resulted in slowing down the operating speed ofthe bus. Conversely, attempts to increase operating speed have typicallyresulted in undesirable increases in power consumption.

Another problem encountered concerns high-performance bus interfacelogic which requires large portions of space on a printed circuit board,leaving less space for the functional logic which must also be mountedon the board.

II. SUMMARY OF THE INVENTION

It is an object of the present invention to provide a backplane bus fora computer system that reduces power consumption while simultaneouslyallowing for high speed operation, and whose bus interface occupiesminimal space on the printed circuit board on which it is mounted.

Another object of the invention is to provide such a backplane bus whichallows direct use with electronic circuits utilizing CMOS (ComplementaryMetal Oxide Semiconductor) technology without need for interfacingthrough non-CMOS devices.

Still another object of the present invention is to increase the numberof backplane bus lines used in such a backplane bus so as to permitduring each cycle of the bus an increase in the quantity of datatransmitted.

A further object of the present invention is to ensure reliableoperation of the computer system which incorporates the inventivebackplane bus arrangement.

Additional objects and advantages of the invention will be set forth inpart in the description which follows and, in part, will be obvious fromthe description or may be learned by practice of the invention. Theobjects and advantages of the invention will be realized and attained bymeans of the instrumentalities and combinations particularly pointed outin the appended claims.

To achieve the objects and in accordance with the purpose of theinvention, as embodied and broadly described herein, the system of thisinvention for transmitting and receiving data between a plurality ofnodes comprises a plurality of nodes, each of which includes logiccircuitry for transmitting and receiving data, a bus for carrying thedata between the nodes, means for individually connecting each of thenodes to the bus, a driver included within the transmitting logic ofeach node for transmitting data onto the bus, means in each node forcoupling the driver to the connecting means for the node, the couplingmeans reducing driver switching noise and power dissipation, permittingdriver overlap at the bus, and for providing impedance matching with thebus, and current source means for the bus for decreasing the transitiontime of the data transmitted onto the bus.

The accompanying drawings, which are incorporated in and constitute partof this specification, illustrate one embodiment of the invention and,together with the description, serve to explain the principles of theinvention.

III. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a data processing system including a systembus and embodying the present invention;

FIG. 2 is a block diagram of a node coupled to a backplane system bus inthe data processing system of FIG. 1;

FIG. 3 is a representative timing diagram showing one bus cycle of thedata processing system of FIG. 1;

FIG. 4 is a block diagram of the data interface used in the nodes ofFIGS. 1 and 2;

FIG. 5 is a block diagram of a central arbiter of the data processingsystem of FIG. 1; and

FIG. 6 is a block diagram of a backplane system bus and exemplary nodesof the data processing system of FIG. 1.

IV. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the presently preferredembodiment of the invention, an example of which is illustrated in theaccompanying drawings. Throughout the drawings, like referencecharacters are used to indicate like elements.

The following discussion is divided into two parts: Section A, whichprovides an overview of the entire data processing system; and SectionB, which provides details regarding the invention specific to theinstant appended claims.

A. System Overview

FIG. 1 shows an example of a data processing system 20 which embodiesthe present invention. The heart of system 20 is a system bus 25 whichis a synchronous bus that allows communication between severalprocessors, memory subsystems, and I/O systems. Communications oversystem bus 25 occur synchronously using periodic bus cycles. A typicalbus cycle time for system bus 25 is 64 nsec.

In FIG. 1, system bus 25 is coupled to two processors 31 and 35, amemory 39, one I/O interface 41 and one I/O unit 51. I/O unit 53, iscoupled to system bus 25 by way of I/O bus 45 and I/O unit interface 41.

A central arbiter 28 is also connected to system bus 25 in the preferredembodiment of data processing system 20. Arbiter 28 provides certaintiming and bus arbitration signals directly to the other devices onsystem bus 25 and shares some signals with those devices.

The implementation shown in FIG. 1 is one which is presently preferredand should not necessarily be interpreted as limiting the presentinvention. For example, I/O unit 53 could be coupled directly to systembus 25, and arbiter 28 need not operate in the manner described for thepresent invention.

In the nomenclature used to describe the present invention, processors31 and 35, memory 39, and I/O interface 41, and I/O device 51 are allcalled nodes. A "node" is defined as a hardware device which connects tosystem bus 25. A typical node 60 is shown in greater detail in FIG. 2.

According to the nomenclature used to describe the present invention,the terms "signals" or "lines" are mainly used interchangeably to referto the names of the physical wires. The terms "data" or "levels" aremainly used to refer to the values which the signals or lines canassume.

Nodes perform transfers with other nodes over system bus 25. A"transfer" is one or more contiguous cycles that share a commontransmitter and common arbitration. For example, a read operationinitiated by one node to obtain information from another node on systembus 25 requires a command transfer from the first to the second nodefollowed by one or more return data transfers from the second node tothe first node at some later time.

A "transaction" is defined as the complete logical task being performedon system bus 25 and can include more than one transfer. For example, aread operation consisting of a command transfer followed later by one ormore return data transfers is one transaction. In the preferredembodiment of system bus 25, the permissible transactions support thetransfer of different data lengths and include read, write (masked),interlock read, unlock write, and interrupt operations. The differencebetween an interlock read and a regular or noninterlock read is that aninterlock read to a specific location retrieves information stored atthat location and restricts access to the stored information bysubsequent interlock read commands. Access restriction is performed bysetting a lock mechanism. A subsequent unlock write command storesinformation in the specified location and restores access to the storedinformation by resetting the lock mechanism at that location. Thus, theinterlock read/unlock write operations are a form of read-modify-writeoperation.

Since system bus 25 is a "pended" bus, it fosters efficient use of busresources by allowing other nodes to use bus cycles which otherwisewould have been wasted waiting for responses. In a pended bus, after onenode initiates a transaction, other nodes can have access to the busbefore that transaction is complete. Thus, the node initiating thattransaction does not tie up the bus for the entire transaction time.This contrasts with a non-pended bus in which the bus is tied up for anentire transaction. For example in system bus 25, after a node initiatesa read transaction and makes a command transfer, the node to which thatcommand transfer is directed may not be able to return the requesteddata immediately. Cycles on bus 25 would then be available between thecommand transfer and the return data transfer of the read transaction.System bus 25 allows other nodes to use those cycles.

In using system bus 25, each of the nodes can assume different roles inorder to effect the transfer of information. One of those roles is a"commander" which is defined as a node which has initiated a transactioncurrently in progress. For example, in a write or read operation, thecommander is the node that requested the write or read operation; it isnot necessarily the node that sends or receives the data. In thepreferred protocol for system bus 25, a node remains as the commanderthroughout an entire transaction even though another node may takeownership of the system bus 25 during certain cycles of the transaction.For example, although one node has control of system bus 25 during thetransfer of data in response to the command transfer of a readtransaction, that one node does not become the commander of the bus 25.Instead, this node is called a "responder."

A responder responds to the commander. For example, if a commanderinitiated a write operation to write data from node A to node B, node Bwould be the responder. In addition, in data processing system 20 a nodecan simultaneously be a commander and a responder.

Transmitters and receivers are roles which the nodes assume in anindividual transfer. A "transmitter" is defined as a node which is thesource of information placed on system bus 25 during a transfer. A"receiver" is the complement of the transmitter and is defined as thenode which receives the information placed on system bus 25 during atransfer. During a read transaction, for example, a commander can firstbe a transmitter during the command transfer and then a receiver duringthe return data transfer.

When a node connected to system bus 25 desires to become a transmitteron system bus 25, that node asserts one of two request lines, CMD REQ(commander request) and RES REQ (responder request), which are connectedbetween central arbiter 28 and that particular node. The CMD REQ and RESREQ lines are shown generally in FIG. 1. In general, a node uses its CMDREQ line to request to become commander and initiate transactions onsystem bus 25, and a node uses its RES REQ line to become a responder toreturn data or message to a commander. Generally, central arbiter 28detects which nodes desire access to the bus (i.e., which request linesare asserted). The arbiter then responds to one of the asserted requestlines to grant the corresponding node access to bus 25 according to apriority algorithm. In the preferred embodiment, arbiter 28 maintainstwo independent, circular queues: one for the commander requests and onefor the responder requests. Preferably, the responder requests have ahigher priority than the commander requests and are handled before thecommander requests.

The commander request lines and responder request lines are consideredto be arbitration signals. As illustrated in FIG. 1, arbitration signalsalso include point-to-point conditional grant signals from centralarbiter 28 to each node, system bus extend signals to implementmulti-bus cycle transfers, and system bus suppression signals to controlthe initiation of new bus transactions when, for example, a node such asmemory is momentarily unable to keep up with traffic on the system bus.

Other types of signals which can constitute system bus 25 includeinformation transfer signals, respond signals, control signals,console/front panel signals, and a few miscellaneous signals.Information transfer signals include data signals, function signalswhich represent the function being performed on the system bus 25 duringa current cycle, identifier signals identifying the commander, andparity signals. The respond signals generally include acknowledge orconfirmation signals from a receiver to notify the transmitter of thestatus of the data transfer.

Control signals include clock signals, warning signals, such as thoseidentifying low line voltages or low DC voltages, reset signals usedduring initialization, node failure signals, default signals used duringidle bus cycles, and error default signals. The console/front panelsignals include signals to transmit and receive serial data to a systemconsole, boot signals to control the behavior of a boot processor duringpower-up, signals to enable modification of the erasable pROM ofprocessors 31, 35 on system bus 25, a signal to control a RUN LIGHT onthe front panel, and signals providing battery power to clock logic oncertain nodes. The miscellaneous signals, in addition to spare signals,include identification signals which allow each node to define itsidentification code.

FIG. 2 shows an example of a node 60 connected to system bus 25. Node 60could be a processor, a memory, an I/O unit or an I/O interface as shownin FIG. 1. In the example shown in FIG. 2, node 60 includes nodespecific logic 65, a node bus 67, and a system bus interface 64containing a data interface 61 and a clock decoder 63. Preferably, datainterface 61, clock decoder 63, and node bus 67 are standard elementsfor nodes connected to system bus 25. The node specific logic 65, whichuses different integrated circuits from system bus interface 64,preferably includes, in addition to the circuitry designed by a user tocarry out the specific function of a node, standard circuitry tointerface with the node bus 67. In general, data interface 61 is theprimary logical and electrical interface between node 60 and system bus25, clock decoder 63 provides timing signals to node 60 based oncentrally generated clock signals, and node bus 67 provides a high speedinterface between data interface 61 and node specific logic 65.

In the preferred embodiment of node 60 and system bus interface 64 shownin FIG. 2, clock decoder 63 contains control circuitry for formingsignals to be placed on system bus 25 and processes clock signalsreceived from central arbiter 28 to obtain timing signals for nodespecific logic 65 and data interface 61. Since the timing signalsobtained by clock decoder 63 use the centrally generated clock signals,node 60 will operate synchronously with system bus 25.

FIG. 3 is a timing diagram showing one bus cycle, the clock signalsreceived by clock decoder 63 from central arbiter 28 (FIG. 1), andcertain of the timing signals generated by clock decoder 63. The clocksignals received by clock decoder 63 include a Time H signal, a Time Lsignal, and a Phase signal as shown in FIG. 3. Time H and Time L areinverses of the fundamental clock signals and the Phase signal isobtained by dividing the fundamental clock signal by three. The timingsignals generated by clock decoder 63 include C12, C23, C34, C45, C56and C61, all of which are shown in FIG. 3. Those timing signals requiredby data interface 61, which occur once per bus cycle, are provided todata interface 61, and a complete set of timing signals, includingequivalent ones of the timing signals provided to data interface 61, isbuffered and provided to the node specific logic 65. The purpose ofbuffering is to insure that node specific logic 65 cannot adverselyaffect the operation of the system bus interface 64 by improperlyloading the timing signals. Clock decoder 63 uses the clock signals tocreate six subcycles for each bus cycle and then uses the subcycles tocreate the six timing signals CXY, where X and Y represent two adjacentsubcycles which are combined to form one timing signal.

Each node in the system bus 25 has its own corresponding set of timingsignals generated by its clock decoder 63. While nominally thecorresponding signals occur at exactly the same time in every nodethroughout the system 20, variations between clock decoder 63 and othercircuitry in multiple nodes introduce timing variations betweencorresponding signals. These timing variations are commonly known as"clock skew."

FIG. 4 shows a preferred embodiment of data interface 61. Data interface61 contains both temporary storage circuitry and bus driver circuitry toprovide a bidirectional and high speed interface between each of thelines of node bus 67 and each of the lines of system bus 25. As shown inFIG. 4, data interface 61 preferably includes storage elements 70 and 72and system bus driver 74 to provide a communication path from node bus67 to system bus 25. Data interface 61 also includes storage element 80and node bus driver 82 to provide communication path from system bus 25to node bus 67. As used in the description of data interface 61, theterm "storage element" refers generally to bistable storage devices suchas transparent latch or a master-slave storage element, and not to aspecific implementation. Persons of ordinary skill will recognize whichtypes of storage elements are appropriate.

As shown in FIG. 4, storage element 70 has an input connected to receivedata from node bus 67 and an output connected to the input of storageelement 72. The output of storage element 72 is connected to an input ofsystem bus driver 74 whose output is connected to system bus 25. Storageelements 70 and 72 are controlled by node bus control signals 76 and 78,respectively, which are derived from the timing signals generated byclock decoder 63. Storage elements 70 and 72 provide a two-stagetemporary storage for pipelining data from node bus 67 to system bus 25.Different numbers of storage stages can also be used.

System bus driver 74 is controlled by system bus drive enable 79.According to the state of the system bus drive enable 79, the input ofsystem bus driver 74 either is coupled to its output, therebytransferring the data at the output of storage element 72 to system bus25, or decoupled from that output. When system bus drive enable 79decouples the input and output of the system bus driver 74, system busdriver 74 presents a high impedance to system bus 25. The system busdrive enable 79 is also generated by clock decoder 63 in accordance withclock signals received from system bus 25 and control signals receivedfrom the node specific logic 65.

Storage element 80 has an input terminal connected to system bus 25 andan output terminal connected to an input of node bus driver 82. Theoutput of node bus driver 82 is connected back to node bus 67. Storageelement 80, preferably a transparent latch, is controlled by a systembus control signal 85 which is derived from the timing signals generatedby clock decoder 63. A node bus drive signal 87 controls node bus driver82 similar to the manner in which system bus drive signal 79 controlssystem bus drive 74. Thus, in response to node bus driver signal 87,node bus driver 82 either couples its input to its output or decouplesits input from its output and provides a high impedance to node bus 67.

In order to explain how data is transferred over system bus 25, it isimportant to understand the relationship between system bus drive enable79 and control signal 85. In the present embodiment, this relationshipis shown in FIG. 3. System bus drive enable 79 is nominally driven fromthe beginning to the end of a bus cycle. The new data become availablefor receipt from system bus 25 at some time later in the bus cycle afterdriver propagation and bus settling time has occurred. In the presentembodiment, storage element 80 is a transparent latch. Control signal 85is logically equivalent to clock C45. The bus timing assures that systembus 25 data is available for receipt sometime prior to the deassertionof control signal 85. Storage element 80 stores bus data that is stableat least a set-up time prior to the deassertion of control signal 85 andremains stable a hold time after the deassertion of control signal 85.

Node bus 67 is preferably a very high speed data bus which allowsbidirectional data transfer between the node specific logic 65 andsystem bus 25 by way of data interface 61. In the preferred embodimentof node 60 shown in FIG. 2, node bus 67 is an interconnect systemconsisting of point-to-point connections between the system businterface 64 and the node specific logic 65. In accordance with thepresent invention, however, there is no requirement for such apoint-to-point interconnection.

FIG. 5 shows a preferred embodiment of the central arbiter 28 which isalso connected to system bus 25. Central arbiter 28 provides the clocksignals for system bus 25 and grants ownership of the bus to the nodeson system bus 25 which request ownership of that bus. Central arbiter 28preferably includes an arbitration circuit 90, a clock circuit 95, and aoscillator 97. Oscillator 97 generates the fundamental clock signals.Clock 95 provides timing signals for arbitration circuit 90 and thebasic Time H, Time L, and Phase clock signals for timing on system bus25. Arbitration circuit 90 receives the commander and responder requestsignals, arbitrates conflicts between nodes desiring access to systembus 25, and maintains the queues referred to above for the commander andresponder requests. Arbitration circuit 90 also provides certain controlsignals to clock 95.

B. The Subject Invention

The present invention will now be explained in detail with particularreference to the preferred embodiment thereof which is illustrated inFIG. 6. As stated previously, like reference characters are usedthroughout the drawings to indicate like elements. Thus, where anelement has been previously identified and discussed, such details willnot be repeated in this section. Instead, reference should be had to theprevious discussion of that element.

In accordance with the present invention, a system is provided fortransmitting and receiving data between a plurality of nodes, each nodeincluding logic circuitry for transmitting and receiving the data, thelogic circuitry being operable from first and second supply voltages.According to a preferred embodiment as illustrated in FIG. 6, the nodesare identified by reference characters 31, 39 and 41 which are examplesof the various nodes depicted in FIG. 1 and discussed above. It shouldbe appreciated, however, that these nodes are merely exemplary ofvarious nodes which can be coupled to the bus 25; thus, no limitationregarding the type of node is intended by the ones illustrated in FIG.6. As shown, each node has the capability of both transmitting andreceiving data.

The nodes 39, 31 and 41 include logic circuitry 80, 80', 100 and 100'which are adapted to operate from first and second supply voltages.Since CMOS technology is employed in the node circuitry for transmittingand receiving data via the bus 25, these supply voltages may correspondto 0 and +5 volts, respectively.

Logic circuitry 80 and 80' each comprises, according to the presentlypreferred embodiment, a CMOS storage element latch 102 (or 102') and aCMOS driver 104 (or 104'). These logic circuits are arranged so as toreceive data for further processing and, thus, the output of drivers104, 104' is coupled to the input of latches 102, 102' which areconnected to control signals 85, 85' previously described. The output oflatches 102, 102' is subjected to further processing, also as describedpreviously.

Logic circuitry 100 of node 41 is adapted, in the illustrated exemplaryembodiment, to transmit data to other devices, e.g., logic circuitry 80,80' of nodes 39, 31. Logic circuitry 100' is similarly adapted totransmit data to such other nodes. This logic circuitry includes, inaccordance with the present invention, a driver for transmitting dataonto the bus. As embodied herein, transmitting circuitry 100,100'includes drivers 74,74' at their respective outputs. These drivers arepreferably CMOS tri-state drivers. A driver is included in the logic ofeach transmitting circuitry in each node connected to the bus.

Circuitry 100 and 100' are also preferably and respectively comprised ofa CMOS storage element or latch 72,72' and control circuitry, such asnode specific logic 65,65' connected by node bus 67,67'. For ease ofdescription, storage element 70 (FIG. 4) has been omitted from FIG. 6.The input of latch 72,72' is connected to logic 65,65' so as to receivedata to be transmitted to other devices within the computer system,while the clock of latch 72,72' is coupled to control 78,78'respectively, as described previously. The output of latch 72,72' isrespectively coupled to the input of driver 74,74' which has a tri-statecontrol, and is connected to Drive signal 79,79' in the manner describedabove. Driver 74,74' provides a high impedance to the bus 25 when Drivesignal 79,79' respectively is inactive.

While not shown in FIG. 6, the devices contained within each of logiccircuitry 80, 80', 100 and 100' are operable from first and secondsupply voltages. In the case of CMOS logic, for example, such supplyvoltages may correspond to +5 and 0 volts, respectively. Thesearrangements are well-known in the art and need not be described furtherfor purposes of understanding the present invention. Additionally, itshould be appreciated that supply levels other than 0 and +5 volts maybe utilized without departing from the spirit or scope of the invention.

In accordance with the present invention, a bus is provided for carryingdata between the nodes. As embodied herein, the bus is indicated in FIG.6 by reference character 25 and may comprise wire, etch or some otherconductor suitable for carrying data present in computer systems. Alsoaccording to the invention, a plurality of means are provided tofacilitate interconnection between bus and the nodes. As embodiedherein, a connector 110 is connected between each node and the bus 25.In this manner, the bus may be disposed in a fixed position in thecomputer system while the nodes are selectively coupled thereto byappropriately plugging each node into a corresponding one of connectors110. Such an arrangement is commonly referred to as a "backplanesystem," with bus 25 being known as a "backplane system bus."

According to the invention, current source means are provided for thebus for decreasing the transition time of the data transmitted onto thebus. As embodied in FIG. 6, the current source means includes a firstresistor 112 and a second resistor 114. Resistor 112 is preferablyconnected between a first end of bus 25 and the first supply voltage,+V, which may be +5 volts in the case of CMOS devices. Resistor 114 ispreferably connected between a second end of bus 25 and the secondsupply voltage, which may be ground as depicted in FIG. 6.

In the presently preferred embodiment, resistors 112 and 114 areeffectively used to terminate the ends of bus 25 such that the busaccelerates the transition between data levels to decrease transitiontimes, as later explained. Thus, other arrangements and equivalentcircuits may be employed in lieu of the illustrated resistors to achievethis function.

Also according to the invention, means are provided in each node forindividually coupling its driver to the connecting means for the nodes,the coupling means providing impedance matching between the bus and thenodes so that driver switching noise is reduced and lower powerdissipation occurs in the drivers. As illustrated in FIG. 6, thecoupling means are identified by reference characters 116, 118 and 120.In the preferred embodiment, each of these means comprises a couplingresistor for coupling nodes 39, 31 and 41, respectively, to bus 25. Asexplained in detail hereinafter, the use of these coupling resistorspermits driver overlap to occur at bus 25.

With respect to the receive circuitry 80, 80' of nodes 39, 31, couplingresistors 116 and 118 are individually coupled between bus 25 and theinput of receivers 104, 104', respectively. With respect to the transmitcircuitry 100,100' of nodes 41,31, coupling resistors 120, 118 arerespectively coupled between bus 25 and the output of tri-state drivers74,74'. According to the presently preferred embodiment, couplingresistors 116, 118 and 120 are each disposed separately, i.e.,externally, to respective drivers 104, 104', 74 and 74'. Further, eachof coupling resistors 116-120 preferably has a resistance that isseveral times, e.g., two to twenty times, the impedance of itscorresponding CMOS driver. Additionally, the value of resistors 112 and114 is selected to be several times, e.g. approximately five times, thevalue of coupling resistors 116-120.

To fully appreciate the operation and concommitant advantages of abackplane bus according to the present invention, reference is made to abus in which the following components are utilized: logic circuits 80,80', 100 and 100' include CMOS drivers 104, 104', 74 and 74' having animpedance in the range of 2 to 10 ohms; resistors 112 and 114 are each150 ohm, 1% tolerance resistors; and coupling resistors 116, 118 and 120are each within the range of 20 ohms to 40 ohms, preferably 30 ohm, 1%tolerance resistors. The supply voltage used is +5 volts, referenced toground.

In operation, data generated, such as by node specific logic 65described previously, are transmitted to bus 25 by transmit circuitry,such as logic circuitry 100 of node 41. These data, in the case of CMOSlogic using 0 and +5 volts, are of a digital nature having recognizablelow and high threshold levels established in the present embodiment at2.0 volts and 3.0 volts, respectively. Such data are carried on bus 25and are received by circuits 80 and 80', for example, which undertakefurther processing on or as a result of the received data. Theadvantages associated with the present invention lie in the manner inwhich the foregoing exchange of data takes place.

Specifically, the foregoing arrangement provides for superior matchingbetween the bus and the nodes connected to it. Firstly, there is amatching in the technology used in that the need for converting fromCMOS logic to other logic (such as TTL) to achieve satisfactory datatransmission is eliminated. This achieves a reduction in circuitryrequired and in various associated costs. Secondly, there is substantialmatching of the impedance of the nodes with that of the bus. In theaforedescribed embodiment, the impedance of each node is approximately30 ohms while the impedance of the bus is in the vicinity of 30 to 60ohms, i.e., only one to two times greater. This impedance matchingallows for better communication of data between the bus and the nodeswith minimal reflection and waste of the energy in the signals.

Use of coupling resistors 116, 118 and 120 which are external to thecorresponding drivers 104, 104', 74 and 74' also provides severaladvantages. The CMOS manufacturing process can alter the impedance ofCMOS drivers virtually anywhere within the range of 2 to 10 ohms. Whenthis impedance is summed with the higher resistance (30 ohms) of therespective coupling resistor, any variation due to the CMOSmanufacturing process is essentially eliminated. This results in a muchmore consistent driver output impedance.

Because of the greater resistance of coupling resistors 116-120 relativeto their respective CMOS drivers, power dissipated within a nodeconnected to bus 25 will chiefly be dissipated via coupling resistors116-120 rather than drivers 104, 104', 74 or 74'. The shifting of thepower dissipation burden from the drivers to the coupling resistorspermits more drivers to be implemented in a single integrated circuitpackage, thus reducing the board area required for the bus interfacelogic. Placing more drivers in the same package however results inincreased noise on the chip power and ground references due to thehigher di/dt of the current through the inductances in the power andground circuits of the package. Traditionally this problem has beensolved by using more pins on the package for power and ground. Theseadditional power and ground pins necessitate the use of higher pin countpackages which in turn require more space on the printed circuit boardfor the bus interface logic. The use of coupling resistors 116, 118, and120 reduce by a factor of 5 to 10 this di/dt and therefore the noiseinduced on the power and ground references, circumventing the need foradditional power and ground pins.

In prior art designs, the timing of the control signals on the busassured that there was never a situation when more than one driver wasdriving the bus at the same time. Otherwise, it was possible that driverdamage would result due to excessive output currents. At a minimum, highlevels of di/dt noise would be generated. In the past, themultiple-driver condition has been avoided by providing a non-overlaptime between the end of the drive time for the previous bus driver andthe beginning of the drive time for the next driver. This need fornon-overlap time increases bus cycle time. The current inventionprovides a novel solution for reducing bus cycle time by allowing thedrive times of the drivers to overlap, yet at the same time avoids theproblems of the prior art such as the risk of driver damage or thegeneration of excessive noise levels. These benefits are the result ofthe coupling resistors which limit the overlap current between any twooverlapping drivers to an acceptable level. Thus, by permitting driveroverlap the portion of the bus cycle time that traditionally wasallotted for non-overlap time can be removed, thereby reducing the buscycle time and increasing performance of the system.

As mentioned previously, the CMOS logic embodied here interprets 2.0volts and lower as a low level and 3.0 volts and higher as a high level.In most prior art devices, buses are employed which swing data levelsfrom one power supply level to the other, i.e., from 0 volts to +5 voltsfor a total swing of 5 volts. In a bus according to the presentinvention, the combined voltage divider effect of resistors 112 and 114with coupling resistors 116-120 causes a reduction in this swing, i.e.,from about 0.8 volt to about 4.2 volts for a total swing of about 3.4volts. Since dynamic power dissipation is proportional to voltagesquared, this improvement in swing correlates to a relative reduction indynamic power dissipation from 25 (5 squared) to 12 (3.4 squared), orabout a 2:1 savings.

Resistors 112 and 114 as stated earlier provide a current source fordecreasing the overall transition time of the bus data from one state toanother. To achieve this reduction in transition time, this currentsource acts in parallel with the driver in the transmitter which isproviding data on the bus. The provision of this current source thussubstantially increases the speed at which the bus can be cycled andthereby increases system performance. Specifically, in this embodiment,resistors 112 and 114 create a Thevenin equivalent circuit of 75 ohmsconnecting the system bus to a nominal 2.5 volts. To illustrate theeffect of this equivalent circuit on bus speed, the equivalent circuitshould be considered in conjunction with the coupling resistors 116-120.Combined, the equivalent circuit and coupling resistors serve toestablish nominal high voltage, voh, and nominal low voltage, vol,levels on the system bus 25 of about 4.2 volts and 0.8 volt,respectively. Since any transition from vol to the high threshold (herenominally 3.0 volts) or from voh to low threshold (here nominally 2.0volts) passes through the 2.5 volt level, the equivalent circuit aidsthe transition by sourcing current for approximately 75% of thetransition time, thus decreasing the time required to make thetransition.

In the present embodiment, variations which occur in the drivers,coupling resistors and current source resistors considered togethercause voh and vol only to vary slightly from their nominal values. Theworst-case voh and vol values are approximately 3.7 and 1.3 volts,respectively. These worst-case values assure an adequate minimum noisemargin of at least 0.7 volt for both logic levels. Noise margin is thedifference between the appropriate receiver input threshold and thedriver output voltage. Adequate noise margins are important for reliablesystem operation and the present invention meets this requirement.

While FIG. 6 illustrates bus 25 as being a single conductor, it shouldbe appreciated from the foregoing description that multiple or parallelbuses can be utilized so as to accommodate data having multiple bits.For example, computer systems having up to 77 parallel bits of data havebeen constructed using backplane bus arrangements according to thepresent invention. That is, 77 buses each being of the type illustratedin FIG. 6 are provided in parallel to accommodate the 77 bits ofinformation contained in the data to be carried on the buses. Additionalbuses can also be provided to accommodate other data, such as commonclocks and control data, which are needed by the system.

Also as discussed previously, the bus is preferably constructed so as tohave connectors 110 which permit nodes 31, 39 and 41 to be selectivelyplugged therein. In this manner, various nodes can be connected to bus25 in order to provide the particular computer system desired by theuser. Conversely stated, the nodes can be provided on "boards" such asprinted circuit cards suitable for plugging into connectors 110. Thisarrangement is shown diagrammatically in FIG. 6 by the dot-dash linesindividually surrounding each of nodes 31, 39 and 41. Such arrangementsare well known in the art and need not be further explained here forpurposes of understanding the present invention.

It will therefore be apparent to those skilled in the art that variousmodifications and variations can be made in the apparatus of the presentinvention. Thus, it is intended that the specification and drawings beconsidered as exemplary only, with the true scope and spirit of theinvention being indicated by the following claims.

What is claimed is:
 1. A system for transmitting and receiving databetween a plurality of nodes via a bus, comprising:a bus having acurrent source; a plurality of nodes, more than one node being capableof driving the bus simultaneously to transfer data, the nodes supplyingtogether with the current source of the bus current for the transfer ofdata such that during such transfer of data the state of the bustransitions between one predetermined voltage level and anotherpredetermined voltage level; means for individually connecting each ofsaid nodes to the bus; a driver in each node designed to supply currentto the bus in parallel with the current source for the transfer of data;coupling resistor means in each node for coupling its driver to theconnecting means for such node, and during occasions when such node isdriving the bus to one predetermined voltage level simultaneously withat least another of the plurality of nodes driving the bus to anotherpredetermined voltage level, for limiting the current flowing throughits driver and avoiding damage to said driver.
 2. A system as recited inclaim 1 wherein said driver in each node is a tri-state driver.
 3. Asystem as recited in claim 2 further comprising logic circuitry in eachnode for transmitting and receiving data via the bus, and wherein thetri-state driver in each node is coupled to the logic circuitry.
 4. Asystem as recited in claim 1 wherein said coupling resistor means ineach node is a coupling resistor having a predetermined resistance valuefor limiting said current flowing through said driver during suchoccasions and chosen also to terminate the bus.
 5. A system as recitedin claim 4 wherein the coupling resistor in each node acts inconjunction with the current source of the bus to limit the transactionsof the bus to the predetermined voltage levels.
 6. A system as recitedin claim 5 wherin the coupling resistor in each node is about 20 to 40ohms.
 7. A system for transmitting and receiving data between aplurality of nodes via a bus, comprising:a bus having a current sourcewhich establishes a nominal voltage level absent any node driving thebus; a plurality of nodes, more than one node being capable of drivingthe bus simultaneously to transfer data, the nodes supplying togetherwith the current source of the bus current for the transfer of data suchthat during such transfer of data the state of the bus transitionsbetween a first predetermined voltage level and a second predeterminedvoltage level passing through said nominal voltage level; means forindividually connecting each of said nodes to the bus; a driver in eachnode designed to supply current to the bus in parallel with the currentsource for the transfer of data; a coupling resistor in each node forcoupling its driver to the connecting means for such node, each couplingresistor having a predetermined resistance value chosen to limit thecurrent flowing through its driver to avoid damage to its driver duringoccasions when such node is driving the bus to the first predeterminedvoltage level simultaneously with at least another of the plurality ofnodes driving the bus to the second predetermined voltage level.
 8. Asystem as recited in claim 7 wherein the driver in each node is atri-state driver.
 9. A system as recited in claim 8 wherein thetri-state driver in CMOS.
 10. A system as recited in claim 9 furthercomprising logic circuitry in each node for transmitting and receivingdata via the bus, and wherein the tri-state driver in each node iscoupled to the logic circuitry.
 11. A system for transmitting andreceiving data between a plurality of nodes via a bus, comprising:a bushaving a current source; a plurality of nodes, more than one node beingcapable of driving the bus simultaneously to transfer data, the nodessupplying together with the current source of the bus current for thetransfer of data such that during such transfer of data the state of thebus transitions between one predetermined voltage level and anotherpredetermined voltage level; means for individually connecting each ofsaid nodes to the bus; logic circuitry in each node for transmitting andreceiving data via the bus; a driver in each node coupled to the logiccircuitry and designed to supply current for the data transfer inparallel with the current source of the bus, such that the currentflowing through such driver is at an acceptable level; linear resistivemeans, having a predetermined resistance value, in each node forcoupling its driver to the connecting means for such node and, duringoccasions when such node is driving the bus to one predetermined voltagelevel simultaneously with at least another of the plurality of nodesdriving the bus to another predetermined voltage level, for preventingthe current flowing through its driver from exceeding said acceptablelevel so as to avoid damage to its driver.
 12. A system as recited inclaim 10, wherein said coupling resistor means comprises a couplingresistor.
 13. A system as recited in claim 10, wherein said currentsource comprises a resistor connected between said bus and said onepredetermined voltage level.
 14. A system as recited in claim 10,wherein said bus has two ends, and said current source comprises firstand second resistors and first and second supply voltages, said firstresistor connecting one end of said bus to said first supply voltage andsaid second resistor connecting the other end of said bus to said secondsupply voltage.
 15. A system as recited in claim 12, wherein said bushas two ends, and said current source comprises first and secondresistors and first and second supply voltages, said first resistorconnecting one end of said bus to said first supply voltage and saidsecond resistor connecting the other end of said bus to said secondsupply voltage.
 16. A system as recited in claim 15 wherein said driveris CMOS.
 17. A system for transmitting and receiving data between aplurality of nodes via a bus, comprising:a bus having two ends and acurrent source, said current source comprising first and secondresistors and first and second supply voltages, said first resistorconnecting one end of said bus to said first supply voltage and saidsecond resistor connecting the other end of said bus to said secondsupply voltage; a plurality of nodes, more than one node being capableof driving the bus simultaneously to transfer data, the nodes supplyingtogether with the current source of the bus current for the transfer ofdata such that during such transfer of data the state of the bustransitions between one predetermined voltage level and anotherpredetermined voltage level; means for individually connecting each ofsaid nodes to the bus; a CMOS tri-state driver in each node designed tosupply current to the bus in parallel with the current source for thetransfer of data; a coupling resistor, having a predetermined resistancevalue, in each node for coupling its CMOS tri-state driver to theconnecting means for such node, and during occasions when such node isdriving the bus to one predetermined voltage level simultaneously withat least another of the plurality of nodes driving the bus to anotherpredetermined voltage level, for limiting the current flowing throughits tri-state driver and avoiding damage to said driver; said couplingresistor in each node acting in conjunction with the current source ofthe bus to limit the transitions of the bus to the predetermined voltagelevels, the predetermined resistance value of the coupling resistorbeing also chosen to terminate the bus; and logic circuitry in each nodefor transmitting and receiving data via the bus, and wherein the CMOStri-state driver in each node is coupled to the logic circuitry.
 18. Asystem for transmitting and receiving data between a plurality of nodesvia a bus, comprising:a bus having a current source; a plurality ofnodes, more than one node being capable of driving the bussimultaneously to transfer data, the nodes supplying together with thecurrent source of the bus current for the transfer of data such thatduring such transfer of data the state of the bus transitions betweenone predetermined voltage level and another predetermined voltage level;means for individually connecting each of said nodes to the bus; logiccircuitry in each node for transmitting and receiving data via the bus;a tri-state driver in each node coupled to the logic circuitry anddesigned to supply current for the data transfer in parallel with thecurrent source of the bus, such that the current flowing through suchdriver is at an acceptable level; a coupling resistor, having apredetermined resistance value, in each node for coupling its tri-statedriver to the connecting means for such node and, during occasions whensuch node is driving the bus to one predetermined voltage levelsimultaneously with at least another of the plurality of nodes drivingthe bus to another predetermined voltage level, for preventing thecurrent flowing through its tri-state driver from exceeding saidacceptable level so as to avoid damage to its tri-state driver.